Minutes of the forward endcap EMC SeeVogh meeting, 25th of April 2016, 15:00-16:30

Presence:

• Basel: Werner
• Bochum: Cathrina, Claudius, Fritz-Herbert, Malte, Matthias, Miriam, Tobias, Tom
• Bonn: Christoph, Matthias, Merlin, Ulrike
• Giessen: Hans-Georg
• Groningen: Myroslav
• GSI: -
• Stockholm: -
• Uppsala: -

APD preamps:

• Modified APD preamps (capacitor across opamp inputs) running smoothly now, even at -25 degrees
• However, so do the unmodfied versions now
• Werner will realize the introduction of a ground layer between top and bottom side of the preamp PCB only if absolutely necessary (heavy modification of PCB)
• In order to further test stability we agreed to equip a full 16-crystal subunit with the new modified APD preamps, as such an array usually is much more ringing prone than single preamps
• Werner waits for gain values to patch a number of 30 existing preamps (we need for one subunit - 2 such preamps we already have) according to our needs (full dynamic range, i.e. 12 GeV energy deposit at 2.2 V output and APD gain of 200)

APD HV single channel regulation:

• Christoph came up with the question of the need of single channel current measurements
• He presented a sketch with positions of the shunt resistor relative to the APD (hot side vs. ground side)
• After some discussion we agreed to not place a shunt with outgoing wires in such highly sensitive part of the circuit
• Hans-Georg reminded us of an idea by Holger using a current mirror and place the shunt in one branch, the APD in the other one
• If that is impossible to realize (space requirement) we may stick with the current monitoring of 8-APD groups only as foreseen in the old design w/o single channel HV trimming
• There was some discussion about the spacial requirement/arrangement of the HV regulation: The limit is the space between backplate and rear forward endcap cover but one may shorted the patch panel PCB studs to gain some space for a HV trimmimg board 'on top' of it, closing the hole in the patch panel board - Christoph is working on that with respect to accessible positions of connectors during assembly

Readout electronics:

• Malte reported that the ADC board/TRB board readout setup is running stable in the lab
• There is a measurement at the Svedberg Lab in Uppsala planned investigating the effect of neutron irradiation to the readout electronics (single event upsets, need for FPGA reflashing).
• The ADC board currently in Bochum will be needed for this tests.
• Stockholm (Markus) will provide the readout, Myroslav and Peter Schakel will attend the measurements in Uppsala.
• So before 'our' ADC will go to Sweden (May 18th) we need to modify (pole zero cancellation) and test the different shaper stage versions
• (There has been some communication between Malte and Pawel after the meeting clarifying what components to change (resistor values))
• BTW: neutron irradiation tests may also be useful for I2C components of the HV trimming, an n-source is available in Giessen, Hans-Georg mentioned

Sorting of VPTTs to specific submodules:

• Ulrike and Christoph presented some plots showing the distributions of VPTT gain, VPTT blue sensitivity index (incl. QE) and B-field gain loss
• All distributions contribute very similar to the total yield, so we will need to account for all of them
• There is about half the batch of VPTTs not yet tested for B-field gain loss. Can we (Bochum) help out with experienced personnel for this task?