Area requirements for cables and cooling pipes

Revision 2 (June 2009)

Due to upcoming discussions at the spring collaboration meeting (March 2009 at GSI) concerning the routing in the backward region of the target spectrometer, the overall detector integration and the connected installation sequence, a revision on the MVD numbers was necessary.
The updated numbers taking into account mechanical aspects (e.g. safety factors) more than detailed cable specifications.
Main goal of this update was:
  • To justify the radius of 150 mm in the upstream region
    which the MVD requests for the routing up to the patch panels
  • To clarify that a higher radius will be occupied after the patch panels.
The numbers of this revision were also presented at the 3rd Mechanics Workshop.
Remark that the main focus is laid on the radial occupancy for the overall MVD routing.
Therefore, the specifications on numbers and types of cables or cooling pipes only serve for an estimation.
They are based on an updated model (close to the one implemented as Mvd-2.0_Pv-3.0_Sv-3.2) w.r.t. the previous revision (especially on the pixel part).

Basic parameters and assumptions

  • Pixel part: Number of frontend chips
    • S-Dk (Small disk layer 1+2): 2 x 20 FEE
    • M-Dk (Medium disks, layer 3-6): 4 x 108 FEE
    • Barrel layer 1: 72 FEE
    • Barrel layer 2: 366 FEE
  • Pixel part: Cabling
    Module controller (MC) merging 2 frontend chips
    2 FEE >> 1 Bus cable
    • ~250 MC for disk part (reduction factor 2.3)
    • ~220 MC for barrel part (reduction factor 2.0)
    • Cable cross section for 1 bus cable: 10 mm x 1 mm
  • Pixel part: Optoelectronic board
    • 1 board for 10 MC's (reduction factor 10)
    • Due to the unknown position of the boards, the area of the cooling pipes are added to the cables
  • Pixel part: Cooling
    • Pipe cross section: 4 mm^2
    • Disk part factor: ~(225 + 25*)
      • 1 pipe / module on disk
      • Doubling due to pipe IN / OUT
      • * Additional cooling for optoelectronic bards: 1 pipe / board
    • Barrel part factor: ~( 70 + 22*)
      • 1 pipe / module
      • Connection of each 2 staves in a barrel (IN / OUT)
      • * Additional cooling for optoelectronic bards: 1 pipe / board
  • Additional safety factor: ~2

  • Strip part, number of frontend chips
    • Forward part (disk layer 5+6): 386 FEE
    • Additional 2 forward disk layers: 386 FEE
    • Barrel 3: 384 FEE
    • Barrel 4: 512 FEE
  • Strip part: cabling
    • 4 FEE >> 1 Bus cable: 320 + 96
    • 1 HV cable / sensor: 1280 +96
    • 1 supply cabel / FEE: 128 +96
    • Cable cross section:
      • 15 mm x 1 mm (Bus)
      • 1.5 mm^2 (HV + FEE supply, respectively)
  • Strip part: Cooling
    • Pipe cross section: 4 mm^2
    • Disk part factor: 48 *48
      • 1 pipe / sensor
    • Barrel part factor: 44
      • 1 pipe / stave
      • Connection of each 2 staves in a barrel (IN / OUT)
  • Additional safety factor: ~2

-- ThomasWuerschig - 03 Jun 2009

Revision 1 (March 2009)

In the table the requirements for the necessary space for cables and cooling pipes between the MVD and the outside of PANDA are given. It is based on the detector design MVD_1.1_Sv2.1_Pv2.1.

The following assumptions have been made:

  • each module has its own power connection for digital and analogue voltage
  • each front-end chip has its own signal lines (i.e. no module controller chip is available)
  • all cables/pipes go from the MVD to a patch panel which sits upstream the EMC endcap
  • on the patch panel the signals are converted from electrical to optical and vice versa. In addition voltage regulators are placed on the patch panel
  • from the patch panel up to the control room the the data is transmitted via optical fibers with a reduction factor of 8
  • the cable/pipe diameters are based on the numbers given in the following document

-- TobiasStockmanns - 23 Mar 2009

Revision 0 (March 2008)

As an answer of the request of Bernd Lewandowski from February 2008 about sub-detector requirements concerning the mass and the cable routing issues I prepared an xls-file (see attachment) with a first version of the needed electrical and thermal services for the MVD.

Note some explanation to the list:

  • Worst case scenario: all cables go upstream to a patch panel upstream the EMC endcap; for each FE chip low readout cables to the patch panel.
  • Assumed 120 pixel modules 1200 FE chips, each chip needs 4 LVDS twisted pair data lines, 1 tw. pair xck, 1 tw. pair serial-in and 2 LV and 1 HV line pair for the power.
  • Assumed 300 strip modules, 250 rectangular and 50 trapezoid with 5 FE per rect. and 4 per trap.; additionally 1 tw. pair xck, 1 tw. pair serial and in and 2 LV and 1 HV line pair for the power.
  • all signal lines go optically from the patch panel to counting room; reduction factor 8 (8 tw.pairs to 1 optical cable) is assumed, serial-in and xck can be put together using BPM protocol.
  • all power lines go on with same multiplicity but the conductor diameter will be increased.
  • no DCS cables included up to now.
  • two additional strip disks further downstream not considered yet; but the cables for them can't be routed like the others, rather they have to go to greater radii (at least r=450mm) outside the CT volume.

-- FabianHuegging - 17 Mar 2008
I Attachment Action SizeSorted ascending Date Who Comment
Subsystemdata_mvd.xlsxls Subsystemdata_mvd.xls manage 16 K 2008-03-17 - 09:53 UnknownUser Routing: Space requirements for the MVD, REVISION 0
SpaceRequirementsCablesCooling_ver1.xlsxls SpaceRequirementsCablesCooling_ver1.xls manage 23 K 2009-06-05 - 16:41 UnknownUser Routing: Space requirements for the MVD, REVISION 1
MVD_SpaceReq_UpstreamRouting_Rev2.xlsxls MVD_SpaceReq_UpstreamRouting_Rev2.xls manage 26 K 2009-06-08 - 16:09 UnknownUser Routing: Space requirements for the MVD, REVISION 2
Topic revision: r15 - 2013-03-25, TommasoQuagli
Copyright © by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding Panda Wiki Send feedback | Imprint | Privacy Policy (in German)