Minutes of the forward endcap EMC eZuce SRN meeting, 27th of February 2017, 14:00-15:15

Presence:

  • Basel: excused
  • Bochum: Cathrina, Claudius, Matthias, Malte, Miriam, Tom, Tobias T.
  • Bonn: excused
  • Groningen: Myroslav
  • Stochholm: -
  • Uppsala: Pawel
  • Giessen: Hans
  • GSI: -

'Shaping time vs. pile-up' studies (Malte):

  • There seems to be something odd in the simulations done:
    • Rising time too steep (2 samples only) compared to real preamp pulses after shaper (2-3 times as much samples), Malte will look into it
  • As the tendering process for the ADC manufacturing is done in some days we need to come to a decision concerning the shaping time for the forward endcap ADC boards.
  • It was decided to repeat Maltes simulations including real noise and meet again on Friday (March, 3rd) to come to a decision.
  • On the Friday meeting we decided for the 2nd highest shaping time resulting in a pile-up probability of about 10% at 50 kHz single crystal rate as expected in the early PANDA-years.
  • At full luminosity the ADC boards may be modified to the second shortest shaping time considered that will give 25 % pile-up events at 500 kHz.
  • If necessary the modification could be done by hand. However, Pawel will look for a possibility for automated replacement.

-- ThomasHeld - 08 Mar 2017
Topic revision: r1 - 08 Mar 2017, ThomasHeld
 
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