You are here: PANDA Wiki>Daq Web>ComputeNode (revision 7)EditAttach

Compute Node Overview

An FPGA-based computational node for PANDA, BESIII and HADES.

For information about old and deprecated versions of the Compute Node, please refer to this page.

Compute Node Version 3 (CNv3):


The so called Compute Node(CN) is foreseen as the FPGA based hardware component of the PANDA DAQ. The third revision of the CN is an ATCA (advanced Telecommunication Computing Architecture) based carrier board. It is able to carry up to 4 xFP boards. The CN is equipped with a Xilinx Virtex 4 FX60, as a switching FPGA to connect the xFP boards in an intelligent way to the backplane. It supplies also direct high speed communications between these boards via rocked I/O.

Daughterboard (xFP)

A xFP board is an extended Telecommunications Computing Architecture (xTCA) compliant board. It is a FPGA based board with a μTCA form factor, featuring a Xilinx Virtex 5 FX70T -2 FPGA, 4 GB DDR2, 1Gb Ethernet, and 4 SFP+ (Small Form- Factor Pluggable) cages. These cages can be equipped for example with optical or RJ45 interfaces.

Edit | Attach | Print version | History: r10 | r8 < r7 < r6 < r5 | Backlinks | View wiki text | Edit WikiText | More topic actions...
Topic revision: r7 - 05 Jun 2014, MilanWagner
This site is powered by FoswikiCopyright © by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding PANDA Wiki? Send feedback
Imprint (in German)
Privacy Policy (in German)